1. Field of the Invention
The present invention relates to semiconductor devices employing simultaneous bi-directional transmission, and methods and apparatus for testing such devices.
2. Description of the Related Art
Semiconductor devices such as processors, controllers, memory devices, etc., are commonly equipped with data transceivers that allow them to receive and transmit digital signals. Conventionally, such transceivers are reconfigurable to either receive or transmit data across an attached transmission line. Recently, devices with simultaneous bi-directional (SBD) transmit/receive capability have received increased interest. As the name alludes to, SBD transceivers have the capability to receive and transmit digital data during the same clock cycle, on the same transmission line.
FIG. 1 shows a conventional SBD connection between two semiconductor devices 20 and 40. Devices 20 and 40 contain, respectively, SBD transceivers 22 and 42. SBD transceiver 22 contains a data driver 24 and a data receiver 26. An internal data signal to be driven, Dout1, is supplied as an input to driver 24 and as a control signal to receiver 26. The output of driver 24 is coupled to the input of receiver 26. Receiver 26 also receives two reference voltages, VrefH and VrefL, which it uses for comparisons, as will be explained shortly. The output of receiver 26 is a data input, Din1, to device 20.
Transceiver 42 of device 40 is preferably matched to transceiver 22 of device 20. Transceiver 42 contains a driver 44 and a receiver 46 connected in an identical configuration as the driver and receiver of transceiver 22. Driver 44 takes its input from an internal data signal Dout2, and receiver 46 generates a data input Din2.
Semiconductor devices 20 and 40 can be connected to each other in the configuration shown in FIG. 1, by connecting the outputs of drivers 24 and 44 to a transmission line 30. Note that in this configuration, the drive state of both driver 24 and driver 44 determine the bit line voltage VBL on transmission line 30. A common reference voltage generator 32 supplies Vref1 and VrefL to both circuits.
FIG. 2 contains waveforms illustrating the simultaneous exchange of data between devices 20 and 40 over transmission line 30. Dout1 is high during time periods T1, T2, and T5. Dout2 is high during time periods T1, T3, and T5. Consequently, during T1, drivers 24 and 44 both pull the bit line voltage VBL high, e.g., to an upper rail voltage Vh. During T2, driver 24 attempts to pull bit line voltage VBL high and driver 44 attempts to pull VBL low, e.g., to a lower rail voltage Vl. With matched drivers, VBL will assume an approximate voltage Vmid, halfway between upper rail voltage Vh and the lower rail voltage Vl. During T3, both drivers reverse, and VBL stays at Vmid. During T4, both drivers pull VBL low, to Vl.
Receivers 26 and 46 determine the drive state of the other device's driver during each time period by selecting an appropriate comparison voltage, based on the known drive state of their own driver. For instance, during T1 and T2, receiver 26 knows that driver 24 is driving line 30 high—thus the only two possible values of VBL are Vh (if driver 44 is also driving line 30 high) and Vmid (if driver 44 is driving line 30 low). Thus during T1 and T2, receiver 26 compares VBL to VrefH, which is midway between Vh and Vmid, and is able to determine that driver 44 was sending a high voltage during T1 and a low voltage during T2. Similarly, during T3 and T4, receiver 26 knows that driver 24 is driving line 30 low, and compares VBL to VrefL. Receiver 46 operates similarly, but based on the known state of driver 44, to determine the drive state of driver 24.
One use of SBD transmission technology is in a point-to-point memory system such as in the partial system depicted in FIG. 3. In such a memory system, devices can communicate with an upstream device and a downstream device over separate connections. For instance, device 20 can be a memory controller, and devices 40 and 60 can be two memory devices connected to the controller. As the controller initiates memory operations, it is upstream of device 40. And as device 40 is interposed between devices 60 and 20, device 40 is upstream of device 60. Address and control signal buses used to control memory operations are not shown in FIG. 3.
Although such a configuration can have any practicable data bus width, FIG. 3 shows a bus width of four bits. One bus consists of point-to-point bit lines 30-0, 30-1, 30-2, and 30-3, with device 20 as an upstream device and device 40 as a downstream device. A second bus consists of point-to-point bit lines 50-0, 50-1, 50-2, and 50-3, with device 40 as an upstream device and device 60 as a downstream device.
Device 40 has an upstream port consisting of four upstream SBD transceivers 42-0, 42-1, 42-2, and 42-3, and a downstream port consisting of four downstream SBD transceivers 48-0, 48-1, 48-2, and 48-3. Within device 40, upstream SBD transceiver is connected to a corresponding downstream SBD transceiver. Thus data received, e.g., at transceiver 42-0, is both a data input Din0 to device 40 and an input Ddn0 to the downstream driver of transceiver 48-0. And data Dup0 received, e.g., at transceiver 48-0, is multiplexed with device 40 output data Dout0 at a multiplexer 45-0, for input to the upstream driver of transceiver 42-0.
Devices 20 and 40 communicate n bits of SBD data as previously described, with the bit lines 30-n working in parallel. Depending on the memory operation, however, the data received by device 40 may be destined either for device 40 or for a downstream device (e.g., device 60), and the data transmitted by device 40 may be either internal data or data received from device 60. Thus devices 20 and 60 communicate data between each other using their respective point-to-point buses to device 40, and device 40 forwards data traffic between its upstream and downstream ports in a pass mode.